Generally, semiconductor devices include a plurality of circuits that form an IC including chips (e.g., chip back end of line, or “BEOL”), thin film packages and printed circuit boards. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (k) organosilicate interlevel dielectric (ILD) layer, such as a carbon doped oxide material including elements of Si, C, H and O (SiCOH), and the fatwires are made in a silicon dioxide ILD having a dielectric constant of about 4. The low k organosilicate ILDs typically have a dielectric constant of less than 3.7. In other structures, either 1× or 2× and/or 4× wires are made in an ultralow dielectric constant (ULK) SiCOH dielectric with k less than 2.6.
For given integration strategies, one of the major challenges associated with the fabrication of thin and fatwires for 90 nm and beyond CMOS BEOL technologies is the issue of ash induced modification of the organosilicate glass (OSG) based ILD materials during damascene processing. This ashing step occurs subsequent to the via (trench) definition in the prior art etching processes. Since the via (trench) structure has already been defined (i.e., created), the chemistry employed to remove the photoresist or other organic material that served as the pattern transfer layer is capable of chemically and physically interacting with the exposed OSG ILD material in the via (trench) structure. Further, since the Si—C (Si—CHx; x=1 to 3) bond of these dense OSG type materials is readily broken, processes known as “de-methylation” or carbon removal by oxygen, nitrogen or hydrogen species can readily occur. These carbon removal reactions are typically energetically favorable and kinetically rapid. ILD modification during the ash process is thus critical, and is very critical for ULK dielectrics.
Because of this issue, several alternative integration schemes have been proposed that circumvent the issue of ash-induced dielectric modification. One such prior art method is disclosed in U.S. Pat. No. 6,734,096 to Dalton, et al. Briefly, in this prior art scheme, the line level is patterned first and subsequently partially defined with the employed photoresist serving as the pattern transfer layer. FIG. 1 is a cross sectional view of an interconnect structure 10 including a trilayer hardmask 18, an antireflective coating 26 and a patterned photoresist 28, in accordance with the disclosure of the '096 patent. As shown, the interconnect structure 10 includes a first dielectric layer 12, a diffusion barrier layer 14 such as a material including elements of C, Si, N and H and a second dielectric layer 16 comprising a low k dielectric material such as an OSG ILD. The trilayer hardmask 18 includes a capping layer 20 comprising elements of Si, C, O and H, a silicon nitride layer 22, and a metallic nitride layer 24, such as TiN or TaN. The patterned photoresist 28 is subsequently removed with the ILD still protected by the metallic nitride layer 24 of the trilayer hardmask 18. A similar procedure is repeated for the via-level with the resist material being removed subsequent to opening the hardmask stack whereby the ILD is again protected by the hardmask layers. The metallic nitride layer 24 of the trilayer hardmask 18 now serves as the pattern transfer layer for the remainder of the dual damascene process; defining the line and via structures. The metallic nitride layer 24 disclosed in the '096 patent offers potential “etch resistance”, sufficient lithography process window, and is re-workable. Such an integration scheme is indeed truly beneficial for avoiding ILD damage due to exposure to various plasma ash chemistries.
However, there are at least 3 problems with the prior art technique disclosed in the '096 patent. First, the etch resistance of the metallic nitride layer 24 is typically insufficient for providing substantial process window in a manufacturing environment. Though one can achieve an excess of 1:1 selectivity for the hardmask layers and SiCOH-based ILD relative to the metallic nitride layer 24, to enable lithography the metallic nitride layer 24 disclosed in the '096 patent must be thin (on the order of about 35 nm or less) and retention of this relatively thin layer is challenging and is nearly impossible. Second, the metal nitride layer 24 is costly to deposit. Third, chlorine-based etch chemistry and metal contaminated etch chambers must be dedicated to pattern the metallic nitride layer 24 of the prior art trilayer hardmask 18. The prior art technique disclosed in the '096 patent avoids ILD damage, but is costly, requires dedicated etch tools, and does not provide a large dual damascene process window.
In view of the above, there is a need to provide a method that circumvents the issue of ash-induced dielectric modification of OSG ILDs, yet circumvents the problems that are inherently present in the '096 patent.